The invention relates to methods used to fabricate semiconductor devices and integrated circuits, and more specifically to a layout and a method of fabrication of a static random access memory (SRAM) cell.
Static random access memory (SRAM) cells, comprised with four N channel metal oxide semiconductor (NMOS) devices and two P channel metal oxide semiconductor (PMOS) devices dissipate less power than counterpart SRAM cells, comprised with either six NMOS devices, or comprised with poly load resistors, when in the stand-by mode of operation. However this type of SRAM cell (four NMOS, two PMOS) results in a significant increase in cell size when compared to counterpart SRAM cells. This invention will describe an SRAM layout comprised with the four NMOS and two PMOS devices, featuring the use of buried contact regions used to connect drain regions of specific devices, thus reducing the area of the SRAM cell when compared to counterpart SRAM cells fabricated using a more area consuming metal contact and interconnect approach. This invention will thereby describe a novel process sequence for fabricating the buried contact regions for both the NMOS and PMOS devices of the SRAM cell, as well as describing the process used to create a dual polycide gate structure, again used to conserve cell area. Prior art such as Yoo et al, in U.S. Pat. No. 5,866,451, as well as Yoo et al, in U.S. Pat. No. 5,719,079, describe methods of fabricating SRAM cells featuring silicide or polycide gate structures. However these prior arts do not describe the novel buried contact regions and dual silicide gate structures featured in this present invention.
It is an object of this invention to fabricate a SRAM cell comprised with four NMOS devices and two PMOS devices.
It is another object of this invention to use buried contact regions to connect drain regions for specific NMOS devices, and to connect the drain regions of specific PMOS devices.
It is still another object of this invention to use a dual polycide gate structure for the NMOS and PMOS devices of the SRAM cell.
In accordance with the present invention the layout and fabrication of an SRAM cell, featuring the use of buried contact regions used to connect drain regions of specific NMOS and PMOS devices of the SRAM cell, and featuring the use of a dual polycide gate structure, is described. After forming a gate insulator layer and an overlying split polysilicon layer, a patterning procedure is employed to remove regions of the split polysilicon layer and the gate insulator layer, exposing areas of a semiconductor substrate to be used for subsequent buried contact regions in both a first region of the semiconductor substrate to be used for the SRAM NMOS devices, and in a second region of the semiconductor substrate to be used for SRAM PMOS devices. A second polysilicon is deposited followed by a patterning procedure forming polysilicon gate structures on the underlying gate insulator layer in both the NMOS and PMOS regions, and forming polysilicon buried contact structures in both the NMOS and PMOS regions, on areas of the semiconductor substrate to be subsequently used for the buried contact regions. Lightly doped source/drain regions, for both NMOS and PMOS devices, are formed in regions of the semiconductor substrate not covered by the polysilicon gate structures or by the polysilicon buried contact structures. After formation of insulator spacers on the sides of all polysilicon gate structures and on the sides of all polysilicon buried contact structures, heavily doped source/drain regions are formed for both NMOS and PMOS device. The dopants used for the heavily doped source/drain regions are also implanted into the polysilicon buried contact structures. A metal silicide layer is next formed on the top surface of all polysilicon gate structures, on the top surface of all polysilicon buried contact structures, and on the top surface of all NMOS and PMOS heavily doped source/drain regions. A post-heavily doped source/drain anneal, in addition to the anneal cycles used for metal silicide formation, result in the formation of the buried contact regions underlying the polysilicon buried contact structure in both the NMOS and PMOS regions. The contact between the buried contact regions underlying the polysilicon buried contact structure, and the adjacent heavily doped source/drain region, allow connection of drain regions of specific NMOS and PMOS devices to occur. Contact holes in an inter-level dielectric layer is followed by formation of metal plug structures, contacting polysilicon buried contact structures, contacting a dual gate polysilicon structure, as well as contacting source/drain regions for both NMOS and PMOS devices. This is followed by a metallization shape resulting in a SRAM cell configuration with four NMOS devices and two PMOS devices, featuring a reduction in the area used for the SRAM cell as a result of the use of buried contact regions used to connect device drain regions.